Computer Organization and Architecture
Instructor
Dr. Janibul Bashir
Course Overview
In this course, we'll study about the architecture and organization of computer systems. We will study about the basic processor designing, pipelining and memory systems.
Course Code
ITT303
Lectures
Mon, Tue, Wed, Thur
Reference Material for the course
Text Book (TB 1): Computer Organisation and Architecture By Smruti Ranjan Sarangi
Text Book (TB 2): Digital Design and Computer Architecture By Harris et al.
Reference (R1): Computer Organisation and Embedded Systems By Carl Hamachar et al.
Reference (R2): Computer Organisation and Design By Patterson et al.
Video Lectures: Computer Organisation and Architecture
Announcements:
The classes have started from 01-08-2023.
[Asssignment 1] - Due Date 01 September
[ASSISGNMENT 2] Design the circuits for the addition, multiplication and division using logism or using any HDL.
Quiz 1 will be held on 05 September at 4:30 PM in PF3 and PF4.
Course Content
Computer Organization and Architecture: The science and art of designing, selecting, and interconnecting hardware components and designing the hardware/software interface to create a computing system that meets functional, performance, energy consumption, cost, and other specific goals.
Introduction to Computer Architecture (TB-Chapter 1, 3, R2-Chapter 1,2)
(01-08-2023) -- [Lecture 1] Course Introduction and Course Structure - [Video Lecture]
(04-08-2023) -- [Lecture 2] Levels of Transformation, Cross Compilation - [Video Lecture]
[Asssignment 1] - Due Date 15 August
(05-08-2023) -- [Lecture 3] What is Architecture and Organization? Computing models: Von Neumann model, Register Based, Registers, Computer architectures - [Video Lecture]
H/W: Learn about the express Memory
Summarize the paper "Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems"
(08-08-2023) -- [Lecture 5] Instruction set Architecture and its components, Microarchitecture and its components - [Video Lecture]
(09-08-2023) -- [Lecture 6] Addressing modes: Register/Memory direct and indirect modes, AutoIncrement, Autodecrement, Immediate, PC relative, and base-index offset - [Video Lecture]
Digital logic: Gates, Registers, and Memories (Reference: TB1 Chapter 6, TB2 Chapter 1,2,3,5)
(10-08-2023) -- [Lecture 7] Digital Logic: Switching Networks, NMOS and PMOS Transistors, Logic Gates, Combinational Circuits - [Video Lecture]
(11-08-2023) -- [Lecture 8] Digital Logic: Switching Networks, NMOS and PMOS Transistors, Logic Gates, Combinational Circuits - [Video Lecture]
(14-08-2023) -- [Lecture 9] Combinational Circuits such as Multiplexer, Decoder, Logic using multiplexers - [Video Lecture]
(18-08-2023) -- [Lecture 10] Programmable Logic Array (PLA), Tristate Buffer
(21-08-2023) -- [Lecture 11] Digital Logic: Sequential Logic, Memory Cells - [Video Lecture]
(22-08-2023) -- [Lecture 12] Digital Logic: Design of a large Memory, Pre-Charging - [Video Lecture]
(23-08-2023) -- [Lecture 13] Digital Logic: DRAM Memory, Refresh Circuit, Concept of a Clock - [Video Lecture]
(24-08-2023) -- [Lecture 14] Digital Logic: Controlling the flow of data using clocks
RISC-V ISA and compilation flow (Reference: RISC-V online documentation)
(28-08-2023) -- [Lecture 15] Introduction to RISC V ISA and Base Integer Version - [Video Lecture]
(30-08-2023) -- [Lecture 16] RV32I Instructions: R/I Format instructions - [Video Lecture1][Video Lecture2]
(01-09-2023) -- [Lecture 17] RV32I instructions: S/U Format instructions - [Video Lecture]
(04-09-2023) -- [Lecture 18] RV32I instructions: - SB/UJ format instructions, RISCV assembly programs - [Video Lecture]
Processor Designing (TB-Chapter 8, R-Chapter 5)
(05-09-2023) -- [Lecture 19] -- Von Neumann Model of Computation for a Processor Design
(06-09-2023) -- [Lecture 20] -- Processor Design: RISC V DataPath, Control Path, Fetch Stage, and Decode Stage - [Video Lecture]
(11-09-2023) -- [Lecture 21] -- Processor Design: Execute, Memory Access, and Register Write-back Stage - [Video Lecture]
(12-09-2023) -- [Lecture 22] -- Processor Design: Design of Control Path, Hardwired and Microprogrammed Control, Horizontal and Vertical Microprogramming - [Video Lecture]
(13-09-2023) -- [Lecture 23] -- Single-Cycle and Multi-Cycle Processors, Thermal Breakdown, Performance Equation - [Video Lecture]
Processor Pipelining (TB-Chapter 9, R-Chapter 6)
(18-09-2023) -- [Lecture 24] -- Processor Pipelining: Uniform Pipeline, Ideal Pipeline, Pipeline Diagram, 5-stage pipeline - [Video Lecture]
(19-09-2023) -- [Lecture 25] -- Pipeline Hazards: Data Hazard, Control Hazard, and Structural Hazard - [Video Lecture]
(09-10-2023) -- [Lecture 26] -- Handling RAW Hazards: Software Solution, Dependency-Check Logic, and Scoreboarding - [Video Lecture]
(10-10-2023) -- [Lecture 27] -- Handling Control Hazards - Stalling Pipeline, Delayed Branching, Branch Prediction - [Video Lecture]
(11-10-2023) -- [Lecture 28] -- Pipeline Hazards Summary | Precise interrupts | Performance Evaluation - [Video Lecture]
Memory System (TB-Chapter 10)
(16-10-2023) -- [Lecture 29] -- Introduction to Memories and Need of a Memory
(17-10-2023) -- [Lecture 30] -- Memory Interleaving: Channels, Ranks, Banks and Memory Arrays
Assignment 3: Design a program that internally executes some other programs (given as input) and verifies the spatial and temporal locality of the executed program.
(18-10-2023) -- [Lecture 31] -- Memory System: On-chip and Off-chip Memory, Principle of Locality, Need of Caches - [Video Lecture]
(19-10-2023) -- [Lecture 32] -- Cache Mapping Techniques: Fully Associative, Direct Mapping, and Set Associative - [Video Lecture]
(20-10-2023) -- [Lecture 33] -- Cache Operations, Write-back, and Write-Through Cache
(25-10-2023) -- [Lecture 34] -- Cache Misses: Compulsory, Capacity, and Conflict Misses, Cache Optimisations: Write Buffer, and Early restart - [Video Lecture]
(26-10-2023) -- [Lecture 35] -- Tutorial related to Caches and Pipelining
MultiProcessor Systems (TB-Chapter 11)
(30-10-2023) -- [Lecture 36] -- Introduction to Multiprocessors, Asymmetric and Symmetric Multiprocessing, Loosely Coupled and Tightly coupled multiprocessors, Multicores - [Multiprocessors]
(31-10-2023) -- [Lecture 37] -- Flynn's classification: SISD, SIMD, MISD, MIMD, Multithreading: coarse-grained, fine-grained, and simultaneous multithreading - [Video Lecture]
(01-11-2023) -- [Lecture 38] -- Amdhal's Law, Utilization, Redundancy and Efficiency of multiprocessor systems.
(02-11-2023) -- [Lecture 39] -- Consistency: Memory Ordering Issues in Multiprocessor Systems.
(06-11-2023) -- [Lecture 39] -- Memory Models: Sequential Consistency, Total Store Order, Relaxed Memory Models
(07-11-2023) -- [Lecture 40] -- Coherence Issues in Multiprocessor Systems
Language of Bits and Computer Arithmetic (TB-Chapter 2, 3, R-Chapter 1, 9) -- SELF READING
(Self Reading 1) -- Representation of Numbers in Decimal, Octal, Hexadecimal and Binary, signed binary number representation, Floating Point Numbers - [Video Lecture1] [Video Lecture2][Video Lecture3]
(Self Reading 2) -- Computer Arithmetic: Binary Addition and Subtraction, Ripple carry adder, Carry Lookahead adder - [Video Lecture]
(Self Reading 3) -- Computer Arithmetic: Multiplication of Binary Numbers, Iterative Algorithm, Booths Algorithm - [Video Lecture]
(Self Reading 4) -- Computer Arithmetic: Binary Division, Restoring Division Algorithm, Non-Restoring Division Algorithm [Video Lecture]
(Self Reading 5) -- Arithmetic operations for floating-point numbers, Truncation: Chopping, Von Neumann Rounding, and rounding - [Video Lecture]
(Self Reading 6) -- Compilation Flow: Compiler, Assembler, Linker and Loader [Video Lecture]
(Self Reading 7) -- Virtual Memory: Overlap Problem, Size Problem, Virtual Memory Map, Virtual Address, Physical Address, Segmentation - [Virtual Mem] [Segmentation]
(Self Reading 8) -- Paging, Page-Tables - Single level, multi-level and Inverted, Translation LookAside Buffer - [Paging]