Dr. Janibul Bashir

Assistant Professor, NIT Srinagar

About Me

I am working as Assistant Professor at the Department of Information Technology, National Institute of Technology Srinagar. My research interests include:

  • Efficient on-chip communication.

  • On-chip security.

  • Parallel and intelligent architectures.

  • Emerging technologies such as photonic on-chip networks, neuromorphic chips etc.

  • Machine Learning

Currently I direct the GAASH research group at NIT Srinagar which primary focuses on system and architecture research. Our research group investigates the effect of new architectural features on the performance of the system. We focus on reducing the power consumption without effecting the performance of the system. Additionally, the group works on enhancing the security of current complex hardware structures. We also work in the field of emerging on-chip technologies such as photonic on-chip networks, and wireless on-chip networks.

The other domains in which our group is working include: application of machine learning techniques in the computer architecture domain (emerging technologies, network-on-chip, thermal management), neuromorphic chips, parallel architectures, and operating systems.

Selected Works

  1. Janibul Bashir, Chandran Goodchild, and Smruti Ranjan Sarangi. "SecONet: A Security Framework for a Photonic Network-on-Chip." In 2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), pp. 1-8. IEEE, 2020.

  2. Janibul Bashir and Smruti Ranjan Sarangi. "Predict, Share, and Recycle Your Way to Low-power Nanophotonic Networks." ACM Journal on Emerging Technologies in Computing Systems (JETC) 16, no. 1 (2019): 1-26.

  3. Janibul Bashir, Eldhose Peter, and Smruti R. Sarangi. "A survey of on-chip optical interconnects." ACM Computing Surveys (CSUR) 51, no. 6 (2019): 1-34.

Events and Accomplishments

  • [Jan 2022]: Research project accepted under SERB SRG scheme.

  • [Oct 2021]: Paper "FreqCounter: Efficient cacheability of encryption and integrity tree counters in secure processors." accepted by Journal of System Architecture.

  • [June 2021]: Paper "Dynamic MTU: A smaller path MTU size technique to reduce packet drops in IPv6" accepted by Journal of Computer and Information Sciences.