VENKATA SAI PRANEETH KAREMPUDI , Janibul Bashir, ISHAN G THAKKAR 2023. An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects. In Journal of Emerging Technologies (JETC 2023)

Tajamul Ashraf, Janibul Bashir, 2023. Climate Change Parameter Dataset (CCPD): A Benchmark Dataset for Climate Change parameters in Jammu and Kashmir In Proceedings of the 4th International Conference on Data Science and Applications (ICDSA 2023)

Shafi, O. and Janibul Bashir, 2021. FreqCounter: Efficient cacheability of encryption and integrity tree counters in secure processors. Journal of Systems Architecture, p.102252. 

Abstract: The data in the off-chip main memory can be potentially extracted or tampered by an adversary having physical access to the device and thus it becomes inevitable to secure the data present in the off-chip memory. The modern designs consider storing the counters on-chip to prevent replay attacks. However, these designs have significant overheads in terms of the on-chip storage used to store counters, and the additional execution time. In this paper, we propose a new mechanism FreqCounter that trims the on-chip storage by storing the counters blockwise in a tag array on-chip cache rather than in a page-wise manner as is conventionally done. The counters for only those blocks are maintained that are expected to miss frequently in the last level cache (LLC). We show that the FreqCounter reduces the space overheads compared to prior schemes by 53.02% keeping performance almost similar if not better. We further show that our design reduces the Energy-Delay Product(ED^2) by 14.5% on an average compared to the recent competing scheme Morphable Counters without any compromise in the security.

Janibul Bashir, and Tahir Ahmad Wani. "Inventive Investment Using Bigdata: Tools, Applicability and Challenges Associated." In Computational Management, pp. 599-627. Springer, Cham, 2021. 

Abstract: Traditional investment models have reached to a saturation level that it is easily recognizable to determine and demonstrate their inadequacy against the current huge data-based investment models. Big Data is taking all management spheres by storm be it marketing, financing or investment. Today colossal and developing volumes of data are being generated and analyzed upon to arrive at meaningful solutions. Big Data analytics joined with the business models can make wonders in the company gains. The Big data analytics will permit organizations to test hypotheses continuously and see the probable outcomes of each hypothesis before bringing the same to the market. This reduces the risks of loss and accelerates the benefits of the organizations tremendously. Insights from large information investigation have the likelihood to empower business process significantly. One important advantage of Big Data analytics is to extract the patterns from the data, and client inclinations and accordingly assist organizations with making effective decisions in business, administrations, and other relevant items. The utilizing of Big Data and machine learning algorithms to dissect the Big information for any association, can take care of issues in different verticals and estimate the business future with more noteworthy speed and unwavering quality. Information investigation has been in the Business Intelligence space for a serious long time giving ‘Point answers’ for explicit issues in any business. The focus of this chapter is to understand these algorithms and their efficacy in the different business scenarios. 

Janibul Bashir, Chandran Goodchild, and Smruti Ranjan Sarangi. "SecONet: A Security Framework for a Photonic Network-on-Chip." In 2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), pp. 1-8. IEEE, 2020. 

Abstract: Photonic networks are already commercially available at the board-level, and many fabrication facilities can fabricate optical networks and integrate them with traditional silicon-based SoCs. Almost all the research in on-chip photonics has been in the areas of performance enhancement and static power reduction. However, before the large-scale adoption of such technologies, it is necessary to solve security problems. As opposed to electrical NoCs, optical NoCs are shared to a much larger extent, and are significantly more sensitive to the latencies of cryptographic operations. Hence, it is necessary to design a novel protocol for securing such networks. We propose a novel, secure, and efficient optical network in this paper (SecONet) that is immune to eavesdropping, spoofing, replay, and message-removal attacks. Using a combination of speculative execution and pre-computation, we reduce the performance overhead of 39.53% with a conventional implementation to 14.2% for a suite of Splash2 and Parsec benchmarks. The additional area overhead of our proposed hardware is modest: 1.6%. 

Janibul Bashir, Khushal Sethi, and Smruti R. Sarangi. "Power efficient photonic network-on-chip for a scalable GPU." In Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, pp. 1-2. 2019. 

Abstract: In this paper, we propose an energy efficient and scalable optical interconnect for GPUs. We intelligently divide the components in a GPU into different types of clusters and enable these clusters to communicate optically with each other. In order to reduce the network delay, we use separate networks for coherence and non-coherence traffic. Moreover, to reduce the static power consumption in optical interconnects, we modulate the off-chip light source by proposing a novel GPU specific prediction scheme for on-chip network traffic. Using our design, we were able to increase the performance by 17% and achieve a 65% reduction in ED2 as compared to a state-of-the-art optical topology. 

Ghosh, Rajib R., Janib Bashir, Smruti R. Sarangi, and Anuj Dhawan. "SpliESR: Tunable power splitter based on an electro-optic slotted ring resonator." Optics Communications 442 (2019): 117-122. 

Abstract: In this paper, we present a novel optical power splitter having an arbitrary split-ratio that can be tuned over a wide range by employing relatively low voltage levels. It is based on a slotted ring resonator. A 120 nm electro-optic polymer-filled slot is created throughout the circumference of the ring. The hybrid ring resonator is made to work between the full and off resonance states, allowing it to work as a power splitter. This is done by changing the refractive index of the electro-optic polymer inside the slot by the application of an external electric field. The splitter combines the electro-optic functionality of the polymer with the high index contrast of the silicon, resulting in a low tuning voltage power splitter. Over a small voltage range of 0–1 V, it is possible to change the split-ratio of this splitter from 0.031–16.738, making it 10 times better than other competing designs. In addition, it takes less than 500 ps to reconfigure the splitter. 

Janibul Bashir, Eldhose Peter, and Smruti R. Sarangi. "A survey of on-chip optical interconnects." ACM Computing Surveys (CSUR) 51, no. 6 (2019): 1-34. 

Abstract: Numerous challenges present themselves when scaling traditional on-chip electrical networks to large manycore processors. Some of these challenges include high latency, limitations on bandwidth, and power consumption. Researchers have therefore been looking for alternatives. As a result, on-chip nanophotonics has emerged as a strong substitute for traditional electrical NoCs.

As of 2017, on-chip optical networks have moved out of textbooks and found commercial applicability in short-haul networks such as links between servers on the same rack or between two components on the motherboard. It is widely acknowledged that in the near future, optical technologies will move beyond research prototypes and find their way into the chip. Optical networks already feature in the roadmaps of major processor manufacturers and most on-chip optical devices are beginning to show signs of maturity.

This article is designed to provide a survey of on-chip optical technologies covering the basic physics underlying the operation of optical technologies, optical devices, popular architectures, power reduction techniques, and applications. The aim of this survey article is to start from the fundamental concepts and move on to the latest in the field of on-chip optical interconnects.

Janibul Bashir and Smruti R. Sarangi. "NUPLet: A Photonic Based Multi-Chip NUCA Architecture." In 2017 IEEE International Conference on Computer Design (ICCD), pp. 617-624. IEEE, 2017. 

Abstract: Area, manufacturing yield and lack of scalable interconnects restrict single chip designs to a small number of cores (16-32). However, multi-chip designs with the help of silicon photonics can overcome area and yield constraints and make it possible to design a virtual chip, which can scale to a large number of cores. Sadly, the scalability of such designs is limited by the high percentage of inter-chip messages and relatively lower hit rate in remote cache banks. In this paper, we propose NUPLet, a multi-chip architecture that tries to remove these limitations by separating the intra and inter chip networks. It proposes to use a non-uniform cache architecture (NUCA) scheme on top of a virtual chip in order to decrease inter chip communication and increase the hit rate in the last level cache. In addition, we propose a prediction mechanism for predicting the number of inter chip messages in the network. This is used to modulate the laser accordingly, and reduce static power consumption. We simulated a four chip based NUPLet design with each chip containing 32 cores. For a suite of Splash2 and Parsec benchmarks, NUPLet increased the last level cache hit rate by 70% as compared to other state of the art proposals. Furthermore, NUPLet improved performance by 28%, reduced power consumption by 39%, and reduced ED 2 by 41%. 

Peter, Eldhose, Anuj Arora, Janibul Bashir, Akriti Bagaria, and Smruti R. Sarangi. "Optical overlay NUCA: A high-speed substrate for shared L2 caches." ACM Journal on Emerging Technologies in Computing Systems (JETC) 13, no. 4 (2017): 1-25. 

Abstract: In this article, we propose using optical networks-on-chip (NoCs) to design cache access protocols for large shared L2 caches. We observe that the problem is unique because optical networks have very low latency, and in principle all of the cache banks are very close to each other. A naive approach is to broadcast a request to a set of banks that might possibly contain the copy of a block. However, this approach is wasteful in terms of energy and bandwidth. Hence, we propose a set of novel schemes that create a set of virtual networks (overlays) of cache banks over a physical optical NoC. We search for a block inside each overlay using a combination of multicast and unicast messages. We first propose two simple protocols: TSI and Broadcast. The former uses unicast messages, and the latter uses multicast messages. We subsequently propose an improved scheme, OP_BCAST, that combines the best of TSI and Broadcast, and mainly uses restricted multicast messages. Then we propose a set of novel hardware structures for creating and managing overlays, for efficiently locating blocks in the overlay, and for implementing dynamically changing overlays with OP_BCAST. The performance of the TSI scheme is within 2% to 3% of a broadcast scheme, and it is faster than traditional schemes with electrical networks by 26%. Compared to the broadcast scheme, it reduces the number of accesses, and consequently the dynamic energy of the caches by 6% to 8%. OP_BCAST is 34% faster than the best solutions with copper-based NoCs; moreover, it reduces the dynamic energy for cache access by 33% compared to the TSI scheme.